1. Field of the Invention
The present invention relates to a PWM communication system used for transmission and reception of data, in which, in a pulse string including pulses having constant cycle, a length of a high level period or a low level period of the pulse is set to correspond to the data.
2. Description of the Prior Art
FIG. 14 is a block diagram showing a structure of a conventional PWM communication system disclosed in, for example, Japanese Patent Publication (Kokai) No. 3-154428. In the drawing, reference numeral 101 is a CPU set on a transmitting system (hereinafter referred to as a transmitting CPU) to transmit a PWM signal to a transmission line 3, 102 is a CPU set on a receiving system (hereinafter referred to as a receiving CPU) to take the PWM signal as input from the transmission line 3, 104 is a power source to feed power required for the transmitting CPU 101 and the receiving CPU 102, 14 is a clock generating portion to feed the transmitting CPU 101 with a clock signal to set a pulse cycle and a data length, and 28 is another clock generating portion to feed the receiving CPU 102 with a clock signal. FIG. 15 is a timing diagram showing one illustrative PWM signal. In FIGS. 15 and 16, reference mark T means a pulse cycle, and t.sub.1, t.sub.2, and t.sub.n are data lengths. In this case, low level periods in the pulses correspond to data.
A description will now be given of the operation. The transmission line 3 is connected to an output port of the transmitting CPU 101 and an input port of the receiving CPU 102. The transmitting CPU 101 sets the level on the output port connected to the transmission line 3 to low. Subsequently, the level on output port is set to high after a lapse of a time corresponding to the data length t.sub.1. Further, after a lapse of time corresponding to the pulse cycle T after the level on the output port is set to low, the transmitting CPU 101 sets the level on the output port to low once again.
Next, the transmitting CPU 101 sets the level on the output port to high after a lapse of time corresponding to the data length t.sub.2. Further, after the lapse of time corresponding to the pulse cycle T after the level on the output port is set to low, the transmitting CPU 101 sets the level on the output port to low again. Similarly, the transmitting CPU 101 sets the level on the output port to high after a lapse of time corresponding to the data length t.sub.n. Further, after the lapse of time corresponding to the pulse cycle T after the level on the output port is set to low, the transmitting CPU 101 sets the level on the output port to low. In such a manner, the PWM signals having the data lengths t.sub.1, t.sub.2, and t.sub.n respectively as shown in FIG. 15 is sequentially transmitted to the transmission line 3.
The receiving CPU 102 takes as input the signal on the transmission line 3 through the input port so as to measure a time interval from a fall time to a rise time of the signal developed at the input port. At the rise time of the signal developed at the input port, in the receiving CPU 102, it is decided that the PWM signal having a data length corresponding to the measured time is received. In such a way, the receiving CPU 102 can receive the data corresponding to the data length in the PWM signal.
In data communication using the PWM signal, an error may be caused in a measured value in the receiving CPU 102 due to a signal delay between the transmitting CPU 101 and the receiving CPU 102, or error between clock signals fed from both the clock generating portions 14 and 28. When the error is caused in the measured value, the receiving CPU 102 may possibly recognize that the receiving CPU 102 receives data different from original data. In order to avoid the possibility, the receiving CPU 102 corrects the measured data lengths t.sub.1, t.sub.2, and t.sub.n.
Referring now to FIG. 16, a description will now be given of a method of correction. The receiving CPU 102 corrects the measured data length t.sub.n according the following expression by using a ratio T/T.sub.c of a measured value T.sub.c between a fall time developed at the input port and the fall time subsequently developed at the input port, to the original pulse cycle T: EQU t.sub.n '=t.sub.n .multidot.(T/T.sub.c)
This can reduce the error of the measured value due to the signal delay or the error of the clock signal. In addition, Japanese Patent Publication (Kokai) No. 3-154428 discloses a method of correction according to the above expression, using a mean value of a plurality of measured values T.sub.c.
Japanese Patent Publication (Kokai) No. 5-292042 discloses another method of reducing the error of the measured value. That is, before transmission of data, a reference pulse is sent from the transmitting system to the receiving system. The receiving CPU measures a width of the reference pulse, and corrects a pulse width of a subsequently received PWM signal by using the measured value and the original width of the reference pulse.
The conventional PWM communication system has the above structure. Thus, it is possible to overcome problems of the steadily generating signal delay and the steadily generating error of the clock signal, and overcome a further problem in that one cycle is expanded or contracted as a whole. However, there is a drawback in that it is impossible to overcome a signal delay or an error of the clock signal, which is temporarily caused within one cycle.
For example, though the transmitting system and the receiving system can recognize an interval between a point A and a point B in FIG. 16 as an identical interval, a point C recognized by the receiving system may temporarily be deviated from the original point C due to some cause. In this case, in the conventional system, data recognized by the receiving system becomes erroneous data in spite of execution of the above correction. As a result, the receiving system can not recognize that the erroneous data is received.